
module isq_idle_pick_dec (
    input [16-1:0]  din,
    output [16-1:0]  dout
);
    
assign dout[0] = din[0]
                 ;
assign dout[1] = din[1]
 & ~din[0]
                 ;
assign dout[2] = din[2]
 & ~din[0]
 & ~din[1]
                 ;
assign dout[3] = din[3]
 & ~din[0]
 & ~din[1]
 & ~din[2]
                 ;
assign dout[4] = din[4]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
                 ;
assign dout[5] = din[5]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
                 ;
assign dout[6] = din[6]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
                 ;
assign dout[7] = din[7]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
                 ;
assign dout[8] = din[8]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
                 ;
assign dout[9] = din[9]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
                 ;
assign dout[10] = din[10]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
                 ;
assign dout[11] = din[11]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
 & ~din[10]
                 ;
assign dout[12] = din[12]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
 & ~din[10]
 & ~din[11]
                 ;
assign dout[13] = din[13]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
 & ~din[10]
 & ~din[11]
 & ~din[12]
                 ;
assign dout[14] = din[14]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
 & ~din[10]
 & ~din[11]
 & ~din[12]
 & ~din[13]
                 ;
assign dout[15] = din[15]
 & ~din[0]
 & ~din[1]
 & ~din[2]
 & ~din[3]
 & ~din[4]
 & ~din[5]
 & ~din[6]
 & ~din[7]
 & ~din[8]
 & ~din[9]
 & ~din[10]
 & ~din[11]
 & ~din[12]
 & ~din[13]
 & ~din[14]
                 ;

endmodule

module isq_age_picker (
input [5:0]      age_0  ,
input                        sel_0  ,
input [5:0]      age_1  ,
input                        sel_1  ,
input [5:0]      age_2  ,
input                        sel_2  ,
input [5:0]      age_3  ,
input                        sel_3  ,
input [5:0]      age_4  ,
input                        sel_4  ,
input [5:0]      age_5  ,
input                        sel_5  ,
input [5:0]      age_6  ,
input                        sel_6  ,
input [5:0]      age_7  ,
input                        sel_7  ,
input [5:0]      age_8  ,
input                        sel_8  ,
input [5:0]      age_9  ,
input                        sel_9  ,
input [5:0]      age_10  ,
input                        sel_10  ,
input [5:0]      age_11  ,
input                        sel_11  ,
input [5:0]      age_12  ,
input                        sel_12  ,
input [5:0]      age_13  ,
input                        sel_13  ,
input [5:0]      age_14  ,
input                        sel_14  ,
input [5:0]      age_15  ,
input                        sel_15  ,
output [5:0]                res_age  ,  
output [4-1:0]            res_index  
);
// Age Comparer Signal Generator
wire [5:0]       age_0_0;
wire                         sel_0_0;
wire [4-1:0]   ind_0_0;
wire [5:0]       age_0_1;
wire                         sel_0_1;
wire [4-1:0]   ind_0_1;
wire [5:0]       age_0_2;
wire                         sel_0_2;
wire [4-1:0]   ind_0_2;
wire [5:0]       age_0_3;
wire                         sel_0_3;
wire [4-1:0]   ind_0_3;
wire [5:0]       age_0_4;
wire                         sel_0_4;
wire [4-1:0]   ind_0_4;
wire [5:0]       age_0_5;
wire                         sel_0_5;
wire [4-1:0]   ind_0_5;
wire [5:0]       age_0_6;
wire                         sel_0_6;
wire [4-1:0]   ind_0_6;
wire [5:0]       age_0_7;
wire                         sel_0_7;
wire [4-1:0]   ind_0_7;
wire [5:0]       age_0_8;
wire                         sel_0_8;
wire [4-1:0]   ind_0_8;
wire [5:0]       age_0_9;
wire                         sel_0_9;
wire [4-1:0]   ind_0_9;
wire [5:0]       age_0_10;
wire                         sel_0_10;
wire [4-1:0]   ind_0_10;
wire [5:0]       age_0_11;
wire                         sel_0_11;
wire [4-1:0]   ind_0_11;
wire [5:0]       age_0_12;
wire                         sel_0_12;
wire [4-1:0]   ind_0_12;
wire [5:0]       age_0_13;
wire                         sel_0_13;
wire [4-1:0]   ind_0_13;
wire [5:0]       age_0_14;
wire                         sel_0_14;
wire [4-1:0]   ind_0_14;
wire [5:0]       age_0_15;
wire                         sel_0_15;
wire [4-1:0]   ind_0_15;
wire [5:0]       age_1_0;
wire                         sel_1_0;
wire [4-1:0]   ind_1_0;
wire [5:0]       age_1_1;
wire                         sel_1_1;
wire [4-1:0]   ind_1_1;
wire [5:0]       age_1_2;
wire                         sel_1_2;
wire [4-1:0]   ind_1_2;
wire [5:0]       age_1_3;
wire                         sel_1_3;
wire [4-1:0]   ind_1_3;
wire [5:0]       age_1_4;
wire                         sel_1_4;
wire [4-1:0]   ind_1_4;
wire [5:0]       age_1_5;
wire                         sel_1_5;
wire [4-1:0]   ind_1_5;
wire [5:0]       age_1_6;
wire                         sel_1_6;
wire [4-1:0]   ind_1_6;
wire [5:0]       age_1_7;
wire                         sel_1_7;
wire [4-1:0]   ind_1_7;
wire [5:0]       age_2_0;
wire                         sel_2_0;
wire [4-1:0]   ind_2_0;
wire [5:0]       age_2_1;
wire                         sel_2_1;
wire [4-1:0]   ind_2_1;
wire [5:0]       age_2_2;
wire                         sel_2_2;
wire [4-1:0]   ind_2_2;
wire [5:0]       age_2_3;
wire                         sel_2_3;
wire [4-1:0]   ind_2_3;
wire [5:0]       age_3_0;
wire                         sel_3_0;
wire [4-1:0]   ind_3_0;
wire [5:0]       age_3_1;
wire                         sel_3_1;
wire [4-1:0]   ind_3_1;
wire [5:0]       age_4_0;
wire                         sel_4_0;
wire [4-1:0]   ind_4_0;

//Input Connection
assign age_0_0 = age_0;
assign sel_0_0 = sel_0;
assign ind_0_0 = 4'd0;
assign age_0_1 = age_1;
assign sel_0_1 = sel_1;
assign ind_0_1 = 4'd1;
assign age_0_2 = age_2;
assign sel_0_2 = sel_2;
assign ind_0_2 = 4'd2;
assign age_0_3 = age_3;
assign sel_0_3 = sel_3;
assign ind_0_3 = 4'd3;
assign age_0_4 = age_4;
assign sel_0_4 = sel_4;
assign ind_0_4 = 4'd4;
assign age_0_5 = age_5;
assign sel_0_5 = sel_5;
assign ind_0_5 = 4'd5;
assign age_0_6 = age_6;
assign sel_0_6 = sel_6;
assign ind_0_6 = 4'd6;
assign age_0_7 = age_7;
assign sel_0_7 = sel_7;
assign ind_0_7 = 4'd7;
assign age_0_8 = age_8;
assign sel_0_8 = sel_8;
assign ind_0_8 = 4'd8;
assign age_0_9 = age_9;
assign sel_0_9 = sel_9;
assign ind_0_9 = 4'd9;
assign age_0_10 = age_10;
assign sel_0_10 = sel_10;
assign ind_0_10 = 4'd10;
assign age_0_11 = age_11;
assign sel_0_11 = sel_11;
assign ind_0_11 = 4'd11;
assign age_0_12 = age_12;
assign sel_0_12 = sel_12;
assign ind_0_12 = 4'd12;
assign age_0_13 = age_13;
assign sel_0_13 = sel_13;
assign ind_0_13 = 4'd13;
assign age_0_14 = age_14;
assign sel_0_14 = sel_14;
assign ind_0_14 = 4'd14;
assign age_0_15 = age_15;
assign sel_0_15 = sel_15;
assign ind_0_15 = 4'd15;

isq_age_cmpr _isq_age_cmpr_0_0(            
.age0        (age_0_0),
.age1        (age_0_1),
.ind0        (ind_0_0),
.ind1        (ind_0_1),
.sel0        (sel_0_0),
.sel1        (sel_0_1),
.res_ind     (ind_1_0),
.res_age     (age_1_0),
.res_rdy     (sel_1_0) 
); 

isq_age_cmpr _isq_age_cmpr_0_1(            
.age0        (age_0_2),
.age1        (age_0_3),
.ind0        (ind_0_2),
.ind1        (ind_0_3),
.sel0        (sel_0_2),
.sel1        (sel_0_3),
.res_ind     (ind_1_1),
.res_age     (age_1_1),
.res_rdy     (sel_1_1) 
); 

isq_age_cmpr _isq_age_cmpr_0_2(            
.age0        (age_0_4),
.age1        (age_0_5),
.ind0        (ind_0_4),
.ind1        (ind_0_5),
.sel0        (sel_0_4),
.sel1        (sel_0_5),
.res_ind     (ind_1_2),
.res_age     (age_1_2),
.res_rdy     (sel_1_2) 
); 

isq_age_cmpr _isq_age_cmpr_0_3(            
.age0        (age_0_6),
.age1        (age_0_7),
.ind0        (ind_0_6),
.ind1        (ind_0_7),
.sel0        (sel_0_6),
.sel1        (sel_0_7),
.res_ind     (ind_1_3),
.res_age     (age_1_3),
.res_rdy     (sel_1_3) 
); 

isq_age_cmpr _isq_age_cmpr_0_4(            
.age0        (age_0_8),
.age1        (age_0_9),
.ind0        (ind_0_8),
.ind1        (ind_0_9),
.sel0        (sel_0_8),
.sel1        (sel_0_9),
.res_ind     (ind_1_4),
.res_age     (age_1_4),
.res_rdy     (sel_1_4) 
); 

isq_age_cmpr _isq_age_cmpr_0_5(            
.age0        (age_0_10),
.age1        (age_0_11),
.ind0        (ind_0_10),
.ind1        (ind_0_11),
.sel0        (sel_0_10),
.sel1        (sel_0_11),
.res_ind     (ind_1_5),
.res_age     (age_1_5),
.res_rdy     (sel_1_5) 
); 

isq_age_cmpr _isq_age_cmpr_0_6(            
.age0        (age_0_12),
.age1        (age_0_13),
.ind0        (ind_0_12),
.ind1        (ind_0_13),
.sel0        (sel_0_12),
.sel1        (sel_0_13),
.res_ind     (ind_1_6),
.res_age     (age_1_6),
.res_rdy     (sel_1_6) 
); 

isq_age_cmpr _isq_age_cmpr_0_7(            
.age0        (age_0_14),
.age1        (age_0_15),
.ind0        (ind_0_14),
.ind1        (ind_0_15),
.sel0        (sel_0_14),
.sel1        (sel_0_15),
.res_ind     (ind_1_7),
.res_age     (age_1_7),
.res_rdy     (sel_1_7) 
); 

isq_age_cmpr _isq_age_cmpr_1_0(            
.age0        (age_1_0),
.age1        (age_1_1),
.ind0        (ind_1_0),
.ind1        (ind_1_1),
.sel0        (sel_1_0),
.sel1        (sel_1_1),
.res_ind     (ind_2_0),
.res_age     (age_2_0),
.res_rdy     (sel_2_0) 
); 

isq_age_cmpr _isq_age_cmpr_1_1(            
.age0        (age_1_2),
.age1        (age_1_3),
.ind0        (ind_1_2),
.ind1        (ind_1_3),
.sel0        (sel_1_2),
.sel1        (sel_1_3),
.res_ind     (ind_2_1),
.res_age     (age_2_1),
.res_rdy     (sel_2_1) 
); 

isq_age_cmpr _isq_age_cmpr_1_2(            
.age0        (age_1_4),
.age1        (age_1_5),
.ind0        (ind_1_4),
.ind1        (ind_1_5),
.sel0        (sel_1_4),
.sel1        (sel_1_5),
.res_ind     (ind_2_2),
.res_age     (age_2_2),
.res_rdy     (sel_2_2) 
); 

isq_age_cmpr _isq_age_cmpr_1_3(            
.age0        (age_1_6),
.age1        (age_1_7),
.ind0        (ind_1_6),
.ind1        (ind_1_7),
.sel0        (sel_1_6),
.sel1        (sel_1_7),
.res_ind     (ind_2_3),
.res_age     (age_2_3),
.res_rdy     (sel_2_3) 
); 

isq_age_cmpr _isq_age_cmpr_2_0(            
.age0        (age_2_0),
.age1        (age_2_1),
.ind0        (ind_2_0),
.ind1        (ind_2_1),
.sel0        (sel_2_0),
.sel1        (sel_2_1),
.res_ind     (ind_3_0),
.res_age     (age_3_0),
.res_rdy     (sel_3_0) 
); 

isq_age_cmpr _isq_age_cmpr_2_1(            
.age0        (age_2_2),
.age1        (age_2_3),
.ind0        (ind_2_2),
.ind1        (ind_2_3),
.sel0        (sel_2_2),
.sel1        (sel_2_3),
.res_ind     (ind_3_1),
.res_age     (age_3_1),
.res_rdy     (sel_3_1) 
); 

isq_age_cmpr _isq_age_cmpr_3_0(            
.age0        (age_3_0),
.age1        (age_3_1),
.ind0        (ind_3_0),
.ind1        (ind_3_1),
.sel0        (sel_3_0),
.sel1        (sel_3_1),
.res_ind     (ind_4_0),
.res_age     (age_4_0),
.res_rdy     (sel_4_0) 
); 


assign res_age   = age_4_0;
assign res_index = ind_4_0;

endmodule


module isq_age_cmpr (
    input [5:0]      age0,
    input [5:0]      age1,
    input [4-1:0]  ind0,
    input [4-1:0]  ind1,
    input                        sel0,
    input                        sel1,
    output [4-1:0] res_ind,
    output [5:0]     res_age,
    output                       res_rdy
);

wire [5:0]      old_age;
wire [4-1:0]    old_ind;
wire                        old_cmp_res;

assign res_rdy = sel0 | sel1;

rob_id_cmpo #(5+1) _rob_id_cmpo(age0,age1,old_cmp_res);

assign old_age = old_cmp_res ? age0 : age1;

assign res_age = {(5+1){~sel1 & sel0}} & age0 |
                 {(5+1){sel1 & ~sel0}} & age1 |
                 {(5+1){sel1 & sel0}} & old_age 
                 ;

assign old_ind = old_cmp_res ? ind0 : ind1;

assign res_ind = {(4){~sel1 & sel0}} & ind0 |
                 {(4){sel1 & ~sel0}} & ind1 |
                 {(4){sel1 & sel0}} & old_ind 
                 ;

endmodule

module isq_entry_num_compute (
input                        entry_vld_0  ,
input                        entry_vld_1  ,
input                        entry_vld_2  ,
input                        entry_vld_3  ,
input                        entry_vld_4  ,
input                        entry_vld_5  ,
input                        entry_vld_6  ,
input                        entry_vld_7  ,
input                        entry_vld_8  ,
input                        entry_vld_9  ,
input                        entry_vld_10  ,
input                        entry_vld_11  ,
input                        entry_vld_12  ,
input                        entry_vld_13  ,
input                        entry_vld_14  ,
input                        entry_vld_15  ,
output [4:0]              entry_num  
);

assign entry_num = entry_vld_0
         + entry_vld_1
         + entry_vld_2
         + entry_vld_3
         + entry_vld_4
         + entry_vld_5
         + entry_vld_6
         + entry_vld_7
         + entry_vld_8
         + entry_vld_9
         + entry_vld_10
         + entry_vld_11
         + entry_vld_12
         + entry_vld_13
         + entry_vld_14
         + entry_vld_15
         ;


endmodule

